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Updates (2016 and Q1 2017)

I did not blog for a while. Here are some updates on what I've been up to in the 15 months since my last blog post:

I've been working on Yosys and formal verification a lot.

In 2016 I've been visiting EasterHack 2016 and gave a long talk about Verilog Synthesis and Formal Verification with Yosys. I've also been to ORCONF 2016 and 33C3 and gave a shorter talk focusing on Formal Verification with Yosys. (I've also been to FOSDEM 2016 and gave a slightly updated version of my 32C3 talk on my Free and Open Source Verilog-to-Bitstream Flow for iCE40 FPGAs.

Earlier this year I've been invited to JKU to give a talk about my current work, focusing on SymbiYosys.

Also in 2016 I finally released PonyLink, a fast single-wire bidirectional interface for connecting FPGAs. I wrote this some time in 2015 but never found the time to clean it up and release it until last summer.

In November 2016 I've been to Berkeley, CA and had many interesting meetings with some great people there (thanks Alan for inviting me). I also met some of the RISC-V crowd in in Berkeley (Aspire Lab at UCB) and San Francisco (SiFive). As a consequence of this I'm now working on https://github.com/cliffordwolf/riscv-formal">riscv-formal, a framework for formally verifying ISA compliance of RISC-V processor cores.

What else? The IcoBoard is finally available for sale online.

Oh, and we won Best Paper Award at ICCAD 2016 with our paper on malicious design flows that inject trojans during synthesis.
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